[Ireland] Postdoctoral Position in Protocol and FPGA design for Passive Optical Networks at Trinity College Dublin
Postdoctoral Position in Protocol and FPGA design for Passive Optical Networks at Trinity College Dublin
Overview
Post-doctoral position in the CTVR Telecommunications Research Centre, School of Computer Science and Statistics, Trinity College Dublin. The work will focus on the implementation of a working protocol in FPGA for Long Reach Passive Optical Networks (LR-PONs). The post will be funded by the CTVR project at Trinity College Dublin but will be based both in Dublin and at the Tyndall Institute in Cork.
Description
Applications are invited for one post-doctoral position in the CTVR Telecommunications Research Centre, School of Computer Science and Statistics, Trinity College Dublin.
The work will focus on the implementation of a working protocol for Long Reach Passive Optical Networks (LR-PONs). The post will be funded by the CTVR project at Trinity College Dublin but will be based both in Dublin and at the Tyndall Institute in Cork.
The overall objective is to implement a fully working PON protocol for a long reach PON including forward error correction (FEC) and electronic dispersion compensation (EDC) operating within the burst mode protocol. It is intended to implement the protocol in FPGA technology. An additional research topic will be the assignment and control, via the protocol, of wavelength tuneable devices to enable full operational wavelength flexibility over the LR-PON network.
The protocol will be developed as an evolution of the ITU GPON protocol and knowledge of the basic principles of that protocol would be an advantage. The PON protocol will be operating at 10Gb/s and will require interface electronics between optical transmitter and receiver modules and the FPGA development boards, electronic design skills will therefore be required. As part of the protocol implementation there will be a requirement to implement (FEC) and electronic (EDC) functions and some knowledge of these techniques would also be an advantage. Basic knowledge of common packet transport protocols such as Ethernet and TCP/IP would also be an advantage.
The successful candidates will have interest, knowledge and experience (including published research papers) in the following areas:
Experience in Xilinx FPGA design
Experience in Verilog and VHDL
Experience in circuit board development
PhD qualification or equivalent post graduate experience in a relevant area
Working knowledge of MAC protocols
Knowledge of the GPON protocol and its implementation will be considered an advantage
The project will be initially to the end of March 2011 with extension to a further three to five years subject to successful project review. After April 2011 the position will be transferred to the Tyndall Institute in Cork.
For application please send a CV with at least two references and motivation letter to:
david.b.payne@btinternet.com, ruffinm@cs.tcd.ie
Research Fields
Engineering - Electronic engineering
Benefits
Salary range: € 37,750 - 46,255
CTVR, University of Dublin, Trinity College – Dublin IRELAND
email ruffinm@cs.tcd.ie
email david.b.payne@btinternet.com http://www.ctvr.ie/
Application Deadline : December, 16th 2010
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